Data processing systems employing a rotating magnetic storage disk in disk drive and a host computer in which data is recorded on and read back from the disk drive are well known in the art. One common type of disk drive used in such a system is a disk drive utilizing a rotating hard disk with a magnetic recording surface. A radially movable read/write head is positioned with respect to any of a number of tracks on the disk using, for example, a voice coil driven servo tracking system.
The signals read by the head from the disk are passed through a read channel amplifier, which amplifies and massages the signals to a pulse form in which each pulse represents a binary bit of information. However, the signals from the read channel amplifier are of variable width, of variable spacing, and unsynchronized. Accordingly, pulse detector circuits are provided for converting the variable width, variable spaced and unsynchronized signals to signals synchronized with clock pulses. For each unsynchronous pulse input, a synchronized pulse is provided by the pulse detector. The synchronized pulses are then provided to a servo signal processor and back to the disk controller. The servo signal processor, under control of a disk controller, then applies signals back to a head positioning controller, preferably in the form of a voice coil driven servo tracking system to properly position the head with respect to a track on the disk for reading or writing in the track.
Typically, each pulse derived from the disk drive represents a binary coded bit of information. As the density of recorded pulses or bits of information increase the rate at which the pulses are transferred to and from the disk drive also increases. With increases in pulse transfer rate and recording density, there are increases in pulse jitter, in variations of intervals between pulses and in variations in pulse width. The widths of the pulses derived from the disk drive are typically controlled by a circuit, which employs an RC time constant, that varies from unit to unit and, even in the same unit, varies with external environment, such as temperature and power supply.
Pulse detectors are commonly employed for detecting the pulses derived from disk drives and for converting these pulses into synchronized pulses of constant width and constant spacing for the host computer.
Pulse detectors are known which receive a train of asynchronous and variable width pulses derived from disk drives and translates them into a train of synchronous constant width pulses. Prior pulse detectors are typically imbedded deeply in the controller or another part of the disk drive system or, for example, a host computer with which it is to operate and cannot be readily isolated from other portions of the system. However, the designs used in prior pulse detectors can generally be divided into two general strategies. One strategy is the generation of a data rate clock to latch or sample incoming pulses. The second strategy is to capture the incoming pulse and digitize it to the closest clock edge.
The first strategy typically involves the use of a phase lock-loop circuit, such as that depicted in FIG. 6. Unsynchronized variable width pulses RDD, derived from a disk drive, are provided to an analog phase lock-loop. A comparator compares the frequency of the RDD pulses with that of the pulses from a voltage control oscillator (VCO). The frequency of the pulses from the VCO are adjusted s that they are synchronized with the RDD input pulses. The clock pulses are then used to transfer the input pulses RDD into flip flops, the outputs of which are decoded and transferred to other storage elements in the system. Once the phase lock is achieved, it is a highly reliable arrangement and is not subject to limitations of pulse detectors using the second strategy (to be discussed). However, the phase lock-loop is subject to the following disadvantages. First, the cost of a reliable phase lock-loop (PLL) is much higher than that of a pulse detector employing the second strategy. Second, if the PLL implementation is of the analog type, it is likely to be effected by environmental conditions, such as temperature. Third, digital type PLLs require significantly higher clock frequency than the incoming pulse rate, making it impractical above certain pulse rates. Fourth, in order to achieve a lock, it requires a precursor of pulses before the phase lock-loop will properly function. However, this approach is still often used, because of its long term reliability, but it is an overdesign for many applications and the high cost is not acceptable. In some cases, a pulse detector utilizing the second strategy is used as a building block for a phase lock loop.
The second strategy is, in general, lower in cost than the first one and is preferred. However, the performance range has typically been limited. Under the second strategy, two different types of implementation techniques have been employed. One being pulse level sensing and the other being pulse edge trigger sensing.
FIG. 7 depicts a prior art level sensing type of pulse detector. In this arrangement a transfer gate is employed, connected between a clock (CLK) and an inverted clock (CLK') with the control gate thereof, connected to the RDD source of unsynchronized variable width pulses derived from a disk drive. The output of the transfer gate is connected to the input of a first inverter. A second inverter is connected from the output back to its input of the first inverter, so as to form a latch. Three or more essentially similar stages, each connected to the output of an inverter of the prior stage, are used to form synchronized signals (TXD), which may be passed to a host computer. This approach checks for the polarity of the incoming signal during one phase of the clock and outputs the result of the sampling in another phase of the clock. Although the circuit has some advantages, such as smaller implementation than edge detectors, a higher tolerance to random noise input than some pulse detectors and the same circuit can be applied to both high pulse rates and low pulse rates, there are significant disadvantages. One disadvantage of the level sensing type pulse detector is its intolerance to input pulse widths which are equal to or narrower than one sampling clock cycle that repeats as fast as or faster than two sampling clock cycles (the Nyquist rate) which is a typical condition in disk drives. Another disadvantage is that the output pulse widths vary with the width of the input pulse.
Edge trigger type pulse detectors, such as that depicted in FIG. 8, detects the rising, or falling, edge of an input pulse and sets a latch. The output of the latch is synchronized by a subsequent circuit with clock pulses, such as CLK. The output of the subsequent circuit is then fed back to the latch to clear it after the signals stored in the subsequent circuit can be reliably read. By way of example, the circuit of FIG. 7 includes D-type flip flops (DFF), a first one of which is triggered by the rising or falling edge of a pulse RDD derived from a disk drive, a second of which is set in response to a signal from the first DFF (caused by the sensing of the edge of the RDD pulse) and a clock pulse CLK and a third, of which is set by the output of the second DFF and a subsequent CLK pulse. The output of the third DFF provides the synchronized constant width pulse TXD used by the rest of the system. FIG. 9 is a schematic representation of the details of a typical DFF design. Although the edge trigger type pulse detector has certain advantages, such as tolerance to narrow input pulse widths and constant output pulse widths, it has significant disadvantages. One disadvantage is that edge triggered flip flops are required which, in turn, require more circuitry than level sensing type circuits. A further disadvantage is that the circuit is intolerant to input pulses which are wider than the output pulse from the edge triggered circuit. More specifically, if the input pulse is wider than the output pulse from the edge triggered pulse detector, more than one synchronized output pulse may result.
In summary, both the level and edge trigger type pulse detectors have drawbacks that limit their operational ranges in terms of input pulse width and output pulse width.
Synchronization concepts are discussed at pages 218-262 of the book Introduction to VLSI Systems, published 1980 by Addison-Wesley Publishing Company, Inc., and the paper entitled "The Behavior of Flip Flops Used as Synchronizers and Prediction of Their Failure Rate," IEEE Journal of Solid State Circuits, Vol. SC-15, No. 2, April 1980.